END IF;
END PROCESS P_DIV;
FOUT<=F_T;
END;
5.如果是用VHDL语言要怎么写呢可以参考 xilinx 的 application note "Serial Code Conversion between BCD and Binary" ponent described above.bcdconvtb.vhd This contains a testbench which applies a serial binary input representing a range of binary numbers, and then writes out the corresponding BCD equivalents----------------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use STD.textio.all; entity BCDConvTB is end; architecture Bench of BCDConvTB is component BCDConv generic (N : positive); port (Clock : in std_logic; Reset : in std_logic; Init : in std_logic; ModIn : in std_logic; ModOut : out std_logic; Q : out std_logic_vector(N*4-1 downto 0) ); end component; -- hold an array of BCD digits type BCDVectorT is array (natural range <>) of std_logic_vector(3 downto 0); -- number of digits implemented in this test bench constant N : positive := 5; -- BCD array as a single std_logic_vector (packed in 4 bits at a -- time) subtype BcdT is std_logic_vector(N*4-1 downto 0); signal Clock : std_logic; signal Reset : std_logic; signal Init : std_logic; -- Initialise BCD conversion signal ModIn : std_logic; -- modulus in, if we wanted to -- cascade lots of NDigits design entities signal ModOut : std_logic; -- modulus out, same reason as ModIn signal Q : BCDT; -- The outputs of the BCD conversion packed -- into a std_logic_vector -- Test bench control signal to ensure Clock stops when testing is over signal StopClock : boolean; -- Outputs of BCD conversion as an array of 4 bit digits. signal BCDVec : BcdVectorT(1 to N); -- Type to allow a table of test values type TableT is array (natural range <>) of Integer; -- some interesting values to test constant Table : TableT := (17,18,19,20,21,22,23,30,40,50, 60,70,80,90,91,92,93,94,95,96, 97,98,99,100,101,302, 555,707,9999,10100, 99999); signal TestInteger : Integer; begin UUT: BCDConv generic map (N => N) port map ( Clock => Clock, Reset => Reset, Init => Init, ModIn => ModIn, ModOut => ModOut, Q => Q); -- 100 ns clock. Clock loop stops automatically when the -- stimulus process has finished, using the boolean signal StopClock ClockGen: process begin while not StopClock loop Clock <= '0'; wait for 50 ns; Clock <= '1'; wait for 50 ns; end loop; wait; end process;-- -- Generate a set of values to test the Binary to BCD converter -- StimGen: process variable TestVal : BCDT; variable L : LINE; begin Reset <= '0'; ModIn <= '0'; Init <= '0'; wait until falling_edge(Clock); Reset <= '1'; wait until falling_edge(Clock); Reset <= '0';-- test all the values in the table write(L, STRING'("Expected:"), LEFT, 10); write(L, STRING'("Actual:"), LEFT, 10); writeline(OUTPUT,L); for I in Table'RANGE loop -- convert integer value to std_logic_vector TestVal := std_logic_vector(to_unsigned(Table(I), N*4)); -- assign the test value to an integer signal - easy to -- disply in the simulator TestInteger <= Table(I); write(L, Table(I), LEFT, 10); -- Loop round all the bits in the input vector for J in BCDT'RANGE loop -- initialise conversion if shifting。
【怎么用VHDL写变频器】
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