<= matlab_in_re;matlab_in_im <= matlab_in_im;endendalways @(posedge clk_100)beginif(mfc_wready && mfc_wvalid)beginmatlab_diff_re <= mfc_wdata_re - matlab_out_re;matlab_diff_im <= mfc_wdata_im - matlab_out_im;matlab_diff_re2 <= matlab_out_re - mfc_wdata_re ;matlab_diff_im2 <= matlab_out_im - mfc_wdata_im ;if(max_diff_re < matlab_diff_re)beginmax_diff_re <= matlab_diff_re;$display("max_diff_re:%d max_diff_im:%d\n",max_diff_re,max_diff_im);endelse if(max_diff_re < matlab_diff_re2)beginmax_diff_re <= matlab_diff_re2;$display("max_diff_re:%d max_diff_im:%d\n",max_diff_re,max_diff_im);endif(max_diff_im < matlab_diff_im)beginmax_diff_im <= matlab_diff_im;$display("max_diff_re:%d max_diff_im:%d\n",max_diff_re,max_diff_im);endelse if(max_diff_im < matlab_diff_im2)beginmax_diff_im <= matlab_diff_im2;$display("max_diff_re:%d max_diff_im:%d\n",max_diff_re,max_diff_im);end$fscanf(fp_matlab_out,"%d, %d\n",matlab_out_re,matlab_out_im);$fwrite(fp_sim_out, "%d, %d\n", mfc_wdata_re,mfc_wdata_im);$fwrite(fp_outdiff, "%d, %d\n",matlab_diff_re,matlab_diff_im);endendendmodule 。
4.求用Verilog写个对应的testbench,指令寄存器的testbench`timescale 1ns/1ps
【verilog怎么写testbench】module reg_tb;
reg [7:0] data_i;
reg ena_i;
reg clk;
reg rst_n;
reg [7:0] cnt;
wire [15:0]opc_iraddr_o;
register DUT(
.clk ( clk ),
.rst ( ~rst_n ),
.data ( data_i ),
.ena ( ena_i ),
.opc_iraddr ( opc_iraddr_o )
);
initial
begin
clk = 0;
rst = 0;
ena_i = 0;
cnt = 0;
data_i = 0;
#50
rst_n = 1;
end
always #5 clk = ~clk;
always @( posedge clk or negedge rst_n )begin
if( !rst_n )
cnt
5.verilog中怎么新建一个testbench`timescale 1ns / 1ps
module tb_dff_s();
reg pi;
reg si;
reg shiftdr;
reg clockdr;
reg updatadr;
reg mode;
wire so;
wire po;
always begin
clockdr = 1'b0;
#5 clockdr = ~clockdr;
#5;
end
always begin
updatadr = 1'b0;
#5 updatadr = ~updatadr;
#5;
end
dff_s uut_dff_s
(
so,
po,
si,
pi,
shiftdr,
mode,
clockdr,
updatadr
);
initial begin
pi = 1'b0;
si = 1'b1;
shiftdr = 1'b0;
mode = 1'b0;
#40;
shiftdr = 1'b1;
#40;
mode = 1'b1;
#40;
pi = 1'b1;
si = 1'b0;
#40;
shiftdr = 1'b0;
#40;
mode = 1'b0;
end
endmodule
6.verilog做38译码器的testbench文件怎么写你好，2113我写5261了一个例子4102你看1653看好了版 。
module tb();reg [2:0] inputD;wire reset; wire clk;wire [7:0] result; initial begin clk =0; clk = #5 ~权clk; endinitial begin reset =0; #20; reset =1; end always @(posedge clk) if reset ==1 begin inputD =3'b000; end else inputD = inputD +1;decode_38 decode_38 (.code(inputD), .result(result));endmodule 。
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